1. Field of the Invention
The present invention relates to voltage regulators, and more particularly to integrated circuit voltage regulators and even more particularly to their response to quickly changing load impedances requiring large, instantaneous, additional load current.
2. Background Information
Voltage regulators are designed to provide a constant DC voltage output, Vref, and are used extensively in integrated circuitry. One operational issue arises in many applications using voltage regulators where a particular circumstance of logic signals or a logic state requires an unusual number of logic circuits or gates to switch in nearly perfect unison. This problem occurs most often in clocked synchronous systems—the type that predominates in logic designs. Typically in such designs, all the logic circuits will switch to or remain in a state in response to a clock edge transition. If all or many gates switch, for example, from a low to a high logic state, the drive transistors, connecting the +Vref to the gate outputs, turn on in unison and drive the output load, especially the load capacitance, high. This load capacitance may be large and the transient current needed to charge this capacitance quickly to a logic high will demand a high transient current from the Vref voltage regulator. There is an impedance of the physical layout and connections between the regulator output and the +Vref rail at the logic circuits, but for this discussion it is not considered because this impedance is typically small and not a major factor in the droop on the +Vref. In any event, the high current quickly demanded by the load manifests as a droop or ripple on the voltage output from the regulator.
Many approaches have been devised to limit this droop. Probably the simplest is a large capacitor (a filter capacitance) on the voltage regulator to supply some of the transient current. But more effective attempts have been made. One such attempt is found in U.S. Pat. No. 5,945,818 by Edwards. In this patent a variable pole/zero configuration is described that provide stability but allowing quick transient response recovery and reduced droop. Another approach is found in U.S. Pat. No. 6,320,363 owned by Motorola, Inc. In this approach dual operational amplifiers are used with differing transient responses that reduce transient voltage droops. Yet another approach is found in U.S. Pat. No. 313,615 owned by Intel Corp. where AC interference is filtered from the DC output to a PLL (phase locked loop).
One issue that must be addressed in any of these designs is the phase margin of the design. Phase margin is the susceptibility or lack of susceptibility of the voltage regulator becoming unstable with projected variable load impedances. Obviously, the regulator must be stable but at the same time respond quickly to changing loads.
There remains a need for a stable voltage regulator that quickly provide fast transient currents with small voltage droops and with sufficient phase margin. Moreover, where space is a premium, for example on the chip, the chip real estate becomes a design issue.